Chip and manufacturing method thereof

ABSTRACT

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

This application is a continuation application of co-pending applicationSer. No. 14/312,443, filed on Jun. 23, 2014, which is a divisionalapplication of U.S. application Ser. No. 13/467,635, filed May 9, 2012,which is a divisional application of U.S. application Ser. No.11/905,482, filed Oct. 1, 2007, which is a continuation-in-partapplication of U.S. application Ser. No. 11/889,879, filed Aug. 17, 2007(now abandoned), which claims the benefit of Taiwan application SerialNo. 95137971, filed Oct. 14, 2006. These related applications areincorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to a semiconductor device and amanufacturing method thereof, and more particularly to a semiconductordevice with fine pitch and a manufacturing method thereof.

2. Description of the Related Art

With the advance in science and technology, various electronic productsare invented and marketed. As the electronic products are widely appliedin everyday life, the demand for semiconductor devices is increasing.Due to the trend of slimness and lightweight in the design ofsemiconductor device, despite the size of a semiconductor device isreduced, the number of I/O actually increases not decreases such thatthe wire pitch and the wire width are both miniaturized. And fine pitchtechnology is thus developed to resolve the above problem.

Referring to both FIG. 1-3. FIGS. 1-2 are side views of a conventionalsemiconductor device 900. FIG. 3 is a top view of a semiconductor device900 of FIGS. 1-2. The semiconductor device 900 is a semiconductor devicewith fine pitch. The semiconductor device 900 includes a plurality ofbonding pads 910 and bumps 920. As indicated in FIG. 1, the bonding pad910 is disposed on an active surface 900 a of the semiconductor device900 and arranged along the direction of X-axis, wherein the bump 920 isa column structure. In the fine pitch technology, the pitch G910 of thebonding pad 910 is as small as 50 um or even under 35 um. As viewed fromthe view-angle of FIG. 3, the bump 920 has a circular cross-sectionparallel to the active surface 900 a.

The column-shaped bump 920 is vertically disposed on the bonding pad910. The semiconductor device 900 is electrically connected to thecontact points (not illustrated in the diagram) disposed on a flip-chipcarrier (normally, the flip-chip carrier is a PCB) via the column bump920 to form a packing structure by a manufacturing process of sealingfor example. Thus, electrical signals are transmitted between theflip-chip carrier and the semiconductor device 900 via the bump 920.

However, during the process of assembling the semiconductor device 900to the flip-chip carrier, the column-shaped bump 920 will bend easilyduring the process of moving or aligning as indicated in the rightmostbump of FIG. 1 and the bump of FIG. 2. Consequently, the semiconductordevice can not be firmly assembled on the flip-chip carrier. To theworse, shortcircuit may occur, severely affecting the electricalfunctions of the packing structure.

The above defected semiconductor device 900 is hard to be re-worked, andis thus wasted. In case the defected semiconductor device 900 can bere-worked, the cost involved is expensive. Therefore, several monitorand inspection systems are employed in the manufacturing process toavoid the defected product going to the next manufacturing process,which may cause an even larger loss. However, the manufacturing processwill incur more costs.

Thus, how to resolve the above problem has become an important issue inthe research and development of semiconductor device.

SUMMARY OF THE INVENTION

According to an aspect of an embodiment of the invention, asemiconductor device and a manufacturing method thereof are provided.The first dimension of the bump is longer than 1.2 times the seconddimension, or the width of the extension of the bump is longer than 1.2times the width of the bonding pad, such that the semiconductor deviceand manufacturing method thereof still possess excellent structuralstrength under the restriction of fine pitches. Thus, the semiconductordevice and manufacturing method thereof disclosed in the aboveembodiments of the invention at least has the advantages of havingenhanced structural strength, improved yield rate and reducedmanufacturing cost.

According to another aspect of an embodiment of the present invention, asemiconductor device is provided. The semiconductor device has an activesurface. The semiconductor device includes at least a bonding pad and atleast a bump. The bonding pad has a minimum dimension smaller than 100microns. The connecting element is disposed on the activate surface andhas a max dimension smaller than 100 microns. The bump is disposed onthe connecting element and is electrically connected to the activesurface by the connecting element. The bump includes a pillar part isdisposed on the connecting element and a top part is disposed at the topof the pillar part. The pillar part has a first dimension and a seconddimension both parallel to the active surface. The first dimension islonger than 1.2 times the second dimension. The top part is composed ofsolder and will melt under the determined temperature. The pillar partwill not melt under a determined temperature.

According to another aspect of an embodiment of the present invention, asemiconductor device is provided. The semiconductor device has an activesurface. The semiconductor device includes a plurality of bonding padsand a plurality of bumps. The bonding pads are disposed on the activesurface. Each of the bumps is disposed on the corresponding bonding pad.Each of the bumps includes a solder part. Wherein there are a pluralityof contact points disposed on a package substrate corresponding to thebumps, the contact points directly contact the solder part, the pitchbetween the contact points is large than the pitch between the bondingpads of active surface.

According to another aspect of an embodiment of the present invention, asemiconductor device is provided. The semiconductor device has an activesurface. The semiconductor device includes a plurality of bonding padsand a plurality of bumps. The bonding pads are disposed on the activesurface. Each of the bumps is disposed on the corresponding bonding pad.Each of the bumps includes a solder part. Wherein there are a pluralityof contact points disposed on a package substrate corresponding to thebumps, the contact points directly contact the solder part, the centerof each of the bump is not directly above the corresponding contactpoint.

According to another aspect of an embodiment of the present invention, amanufacturing method of semiconductor device is provided. Thesemiconductor device includes a bonding pad disposed on an activesurface of the semiconductor device. The manufacturing method ofsemiconductor device at least includes the following steps. Firstly, afirst metal layer is deposited above the bonding pad and part of theactive surface, wherein the first metal layer has a first dimension anda second dimension both parallel to the active surface, the firstdimension is longer than 1.2 times the second dimension, and the firstmetal layer will not melt under a pre-determined temperature. Secondly,a second metal layer is formed above the first metal layer, wherein thesecond metal layer will melt under the pre-determined temperature, andthe first metal layer and the second metal layer form a bump.

According to another aspect of an embodiment of the present invention, amanufacturing method of semiconductor device is provided. Themanufacturing method of semiconductor device at least includes thefollowing steps. Firstly, a die is provided, wherein the die includes abonding pad disposed on an active surface of the die. Secondly, a UBMlayer is formed on the bonding pad under an inert gas environment.Thirdly, a photosensitive material is formed on the UBM layer and theactive surface and the photosensitive material is patterned to form atleast an opening for exposing the UBM layer and part of the activesurface. Fourthly, the die is placed in a solution including first metalions, wherein the solution includes copper ions (Cu⁺⁺), sulfuric acid(H₂SO₄) and chloride ions, the copper ions have a concentration between10˜40 gram/liter, the sulfuric acid has a concentration between 120˜300gram/liter, the chloride ions have a concentration between 30˜70 ppmsuch that a first metal layer is electroplated in the opening, whereinthe first metal layer contacts the UBM layer. Fifthly, a second metallayer is underfilled in part of the opening, wherein the second metallayer contacts the first metal layer, such that the first metal layerand the second metal layer form a bump. Lastly, the photosensitivematerial is removed.

According to another aspect of an embodiment of the present invention, asemiconductor device is provided. The semiconductor device comprise atleast a connecting element and at least a bump. The connecting elementhas a minimum dimension smaller than 100 microns, wherein the connectingelement is disposed on the active surface. The bump is disposed on theconnecting element and electrically connected to the active surface bythe connecting element, wherein the bump comprises a pillar partdisposed on the connecting element and a top part disposed at the top ofthe pillar part, the pillar part has a first dimension and a seconddimension both parallel to the active surface, the first dimension islonger than 1.2 times the second dimension, the top part is composed ofsolder and will melt under the pre-determined temperature, and thepillar part will not melt under a determined temperature. Wherein thematerial of the pillar part is selected from a group consisting ofcopper (Cu), gold (Au), nickel (Ni) or a combination thereof, and thetop part extending toward the top of the pillar part and disposedthereon is made from tin (Sn)-lead (Pb) or any lead free solders.

According to another aspect of an embodiment of the present invention, asemiconductor device with an active surface is provided. Thesemiconductor device comprises a plurality of bonding pads and aplurality of bumps. The bonding pads are disposed on the active surface.The bumps are disposed on the bonding pads respectively, wherein eachbump comprises a pillar part disposed on the bonding pad and a top partcomposed of solder solder, the top part is disposed on the top of thepillar part, and the connecting lines of the bonding pads and the bumpsare arranged in off-centered arrangement.

The invention with the above advantages and other advantages will becomeapparent from the following detailed description of the preferredembodiment. The following description is made with reference to theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

(Prior Art) FIGS. 1˜2 are side views of a conventional semiconductordevice;

(Prior Art) FIG. 3 is a top view of a semiconductor device of FIGS. 1-2;

FIGS. 4˜5 are side views of a semiconductor device according to a firstembodiment of the invention;

FIG. 6 is a top view of a semiconductor device of FIGS. 4˜5;

FIG. 7 is a flowchart of a method for manufacturing a semiconductordevice according to a preferred embodiment of the invention;

FIG. 8 is detailed flowchart of a method for manufacturing asemiconductor device according to a preferred embodiment of theinvention;

FIGS. 9A˜9F illustrate each step of the method for manufacturing a bumpand a semiconductor device using the same;

FIG. 10 is a top view of a die and a photosensitive material of FIG. 9C;

FIG. 11 illustrates the disposition of a bump of a semiconductor deviceaccording to a second embodiment of the invention; and

FIG. 12 illustrates the disposition of a bump of a semiconductor deviceaccording to a third embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

Referring to both FIG. 4˜6. FIGS. 4˜5 are side views of a semiconductordevice 100 according to a first embodiment of the invention. FIG. 6 is atop view of a semiconductor device of FIGS. 4˜5. As indicated in FIG. 4,the semiconductor device 100 has an active surface 100 a and includes atleast a bonding pad 110 and at least a bump 120. The bonding pad 110disposed on the active surface 100 a is a connecting element forelectrically connecting the active surface 100 a to the bump 120. Thebump 120 is vertically disposed on the bonding pad 110. As indicated inFIG. 6, the bump has a first dimension D121 and a second dimension D122both parallel to the active surface 100 a, wherein the first dimensionD121 is illustrated in FIG. 5 and FIG. 6, and the second dimension D122is illustrated in FIG. 4 and FIG. 6. The first dimension D121 is longerthan 1.2 times the second dimension D122. As the structural strength ofminiaturized elements is emphasized in the present embodiment of theinvention, the shorter dimension of the bump 120 (the second dimensionin the present embodiment of the invention) should be smaller than 100microns. The minimum dimension of the bonding pad 110 is preferablysmaller than the minimum dimension of the bump 120, that is, smallerthan 100 microns, and the minimum dimension of the bonding pad 110 ispreferred to be smaller than 80 microns. Meanwhile, the cross-section ofthe bonding pad 110 is preferred to be symmetric with respect to thecenter. For example, the shape of the cross-section is circular,squared, diamond-shaped, rectangular or elliptical, but is not limitedthereto. Further, as shown in said drawings, the extending center lineof the bonding pad 110 disposed in the active surface 100 a and theextending center line of the bump 120 are not the same. That is, theconnecting lines of the boding pads 110 and the bumps 120 are disposedin an off-centered arrangement.

In the present embodiment of the invention, the first dimension D121 isperpendicular to the second dimension D122, wherein the first dimensionD121 is the maximum dimension of the bump 120 parallel to the activesurface 100 a, and the second dimension D122 is the minimum dimension ofthe bump 120 parallel to the active surface 100 a. As indicated in FIG.6, the cross-section of the bump 120 parallel to the active surface 100a is preferably an I-shaped structure but is not limited thereto.Normally, the I-shaped bump 120 is stronger than the column-shaped bump.

Besides, as indicated in FIG. 6, one end of the bump 120 at leastextends from the bonding pad 110 in a direction C1 (the direction of theY-axis). The extending direction C1 is parallel to the active surface100 a, and the length D121 of the extending direction C1 of the bump 120is longer than 1.2 times the width D110 of the bonding pad 110. In thepresent embodiment of the invention, the length D121 of the extendingdirection C1 of the bump 120 is equivalent to the maximum dimension D121of the bump 120. That is, the bump 120 not only covers the bonding pad110 but also extends in the direction C1.

Moreover, the edge of the bump 120 covers the bonding pad 110, and theother part of the bump 120 covers part of the active surface 100 a. Thebump 120 contacts the active surface 100 a by an area larger than 1.2times the area of the bonding pad 110. Therefore, under the trend ofminiaturization in the design of the semiconductor device 100, despitethe dimension and the pitch of the bonding pad 110 are reduced, the bump120 still maintains a certain level of structural strength.

As indicated in FIG. 5, the comparison between the width D110 of thebonding pad 110 and the height H120 of the bump 120 shows that theheight H120 of the bump 120 is preferably larger than the width D110 ofthe bonding pad 110. As the conventional bump 920 can only cover thebonding pad 910 (the bump 920 and the bonding pad 910 are illustrated inFIG. 1), the bump 920 is slim and will tilt or bend easily. The bump 120of the invention not only covers the bonding pad 110, but also extendsfrom the bonding pad 110 in the direction C1 and further covers part ofthe active surface 110 a, such that the bump 120 has a strong structureand will not tilt or bend easily.

Referring to FIG. 5 again. The bump 120 includes a pillar part 121 and atop part 122. The bottom of the pillar part 121 is disposed on thebonding pad 110, and the top part 122 is disposed at the top of thepillar part 121 and extends toward the top of the pillar part 121. Thetop part 122, which will melt and reflow under the pre-determinedtemperature, can be selected from a group consisting of solder, tin(Sn)-lead (Pb) or any lead free solder. Under a pre-determinedtemperature, the pillar part 121 will not melt and the material thereofis selected from a group consisting of copper (Cu), gold (Au), nickel(Ni) or a combination thereof, wherein copper is preferred in thepresent embodiment of the invention. The manufacturing method of thepillar part 121 and the top part 122 of the bump 120 is exemplified inFIG. 7.

Referring to both FIG. 7 and FIGS. 9A˜9F. FIG. 7 is a flowchart of amethod for manufacturing a semiconductor device according to a preferredembodiment of the invention. FIGS. 9A˜9F illustrate each step of themethod for manufacturing a bump and a semiconductor device using thesame. The manufacturing method of the bump of the invention and asemiconductor device using the same at least includes the following twosteps.

Firstly, the method begins at step S701. As indicated in FIGS. 9A˜9D, afirst metal layer 151 is deposited on the bonding pad 110 and part ofthe active surface 100 a, wherein the first metal layer 151 has a firstdimension D121 and a second dimension D122 both parallel to the activesurface 100 a, and the first dimension D121 is longer than 1.2 times thesecond dimension D122. That is, the second dimension D122 of the firstmetal layer 151 is equivalent to the second dimension D122 of FIG. 5.The material of the first metal layer 151 is selected from a groupconsisting of copper, gold, nickel or the alloy thereof. That is, thematerial of the first metal layer 151 is selected from the same groupwith that of the pillar part 121 to form the above pillar part 121. Thefirst metal layer 151 can be deposited by a semi-conductor manufacturingprocess such as electroplating, evaporating or sputtering.

Secondly, the method proceeds to step S702. As indicated in FIGS. 9E˜9F,a second metal layer 152 is formed above the first metal layer 151, suchthat the first metal layer 151 and the second metal layer 152 form thebump 120. The material of the second metal layer 152 is selected from agroup consisting of tin(sn)-lead(Pb) or any lead free solder. That is,the material of the second metal layer 152 is selected from the samegroup with that of the top part 122 to form the above top part 122,wherein the second metal layer 152 is mainly composed of solder. Thesecond metal layer 152 can be underfilled by a manufacturing processsuch as electroplating, evaporating or sputtering or printing.

The manufacturing method of the semiconductor device 100 of the presentembodiment of the invention is exemplified by a plurality ofsemi-conductor manufacturing processes. Referring to both FIG. 8 andFIGS. 9A˜9F. FIG. 8 is a detailed flowchart of a method formanufacturing a semiconductor device 100 according to a preferredembodiment of the invention.

Firstly, the method begins at step S801 of FIG. 8. As indicated in FIG.9A, a die 160 is provided, wherein the die 160 includes a bonding pad110 disposed on the active surface 100 a of the die 160. In themanufacturing process of semi-conductor, the die 160 is formed bydividing a wafer. Normally, the wafer is used as a manufacturing unit,and the wafer is divided into a plurality of semiconductor devices 100after the bump 120 is formed.

Next, the method proceeds to step S802 of FIG. 8. As indicated in FIG.9B, under an inert environment, an under bump metallurgy (UBM) layer 130is formed on the bonding pad 110 and the entire active surface 100 ausing sputtering or evaporation. An apparatus is used to vacuum thechamber to achieve the level of 1×10−7 torr˜1×10-8 torr. The pressureinside the chamber can be appropriately adjusted according to actualneeds during the manufacturing process. In the present embodiment of theinvention, preferably, the apparatus vacuums the chamber to achieve alevel of 5×10-7 torr˜1×10-8 torr. Then, argon is infused to the chamberuntil the pressure inside the chamber reaches few millitorr upto 100millitorr, and the manufacturing process of sputtering is performedunder the inert gasenvironment.

In step S802, titanium (Ti), copper (Cu), wolfram (W), nickel (Ni)palladium (Pd) or gold (Au) is used as a target material for sputteringor evaporating a titanium-copper (Ti—Cu) stacked structure, atitanium-wolfram-copper (Ti—W—Cu) stacked structure, a titanium-nickel(Ti—Ni) stacked structure or a titanium-palladium-gold (Ti—Pd—Au)stacked structure to form the UBM layer 130. The UBM layer 130 iscomposed of an adhesive layer, a barrier layer or a wetting layer, andthe material for the UBM layer 130 is determined according to the designof the product.

Next, the method proceeds to step S803 of FIG. 8. As indicated in FIG.9C, a photosensitive material 140 is formed on the UBM layer 130 and theactive surface 100 a. The photosensitive material 140 is patterned toform at least an opening 140 a for exposing the UBM layer 130 and partof the active surface 100 a.

Referring to FIG. 10, a top view of a die 160 and a photosensitivematerial 140 of FIG. 9C is shown. In step S803, the opening 140 a has afirst inner diameter D141 and a second inner diameter D142 both parallelto the active surface 100 a, wherein the first inner diameter D141 islonger than 1.2 times the second inner diameter D142. That is, thecross-section of the opening 140 a parallel to the active surface 100 ais an I-shaped structure. The bonding pad 110 and the UBM layer 130 arepositioned at the edge of the opening 140 a, wherein the bonding pad 110is covered under the UBM layer 130 and is indicated in dotted line inFIG. 10. The area of the opening 140 a is preferably longer than 1.2times the area of the bonding pad 110. The opening 140 a extends fromthe bonding pad 110 in a direction C1, wherein the length D141 of theextending direction C1 of the opening 140 a is longer than 1.2 times thewidth D110 of the bonding pad 110. That is, the extended length D141 ofthe opening 140 a is equivalent to the first inner diameter D141 of theopening 140 a.

Next, the method proceeds to step S804 of FIG. 8. As indicated in FIG.9D, the die 160 is placed into a solution including the first metal ionsso as to electroplate the first metal layer 151 in the opening 140 a.The first metal layer 151 contacts the UBM layer 130. In the presentembodiment of the invention, the solution includes copper ions (Cu),sulfuric acid (H₂SO₄) and chloride ions to form the first metal layer151 whose material includes copper.

In step S804, copper ions have a concentration between 10˜40 gram/liter,sulfuric acid has a concentration between 120˜300 gram/liter, chlorideions have a concentration between 30˜70 ppm. The components andconcentrations of the solution can be adjusted and controlled accordingto the machine parameters and the to-be-formed first metal layer 151. Inthe present embodiment of the invention, the operating temperature ispreferably set to be 20˜30° C., and the concentration of the copper ionsis controlled to be between 20˜35 gram/liter, the concentration of thesulfuric acid is controlled to be between 150˜250 gram/liter, theconcentration of the chloride ions is controlled to be between 35˜60ppm.

The area of the opening 140 a is larger than 1.2 times the area of thebonding pad 110. Therefore, when the first metal layer 151 is formed inthe opening 140 a, the area of the part of the active surface 100 acovered by the first metal layer 151 is larger than the area of the partof the active surface covered by the bonding pad 100. Preferably, thefirst metal layer 151 contacts the active surface 100 a by an arealarger than 1.2 times the area of the part of the active surface coveredby the bonding pad 100.

Then, the method proceeds to step S805 of FIG. 8. As indicated in FIGS.9E˜9F, the second metal layer 152 is underfilled to part of the opening140 a, and the second metal layer 152 contacts the first metal layer151. Next, the second metal layer 152 is reflown, such that the firstmetal layer 151 and the second metal layer 152 form a bump 120 asindicated in FIG. 9F. The ways of underfilling the second metal layer152 include electroplating, evaporating, sputtering and printing.

Next, as indicated in FIG. 9F, the above photosensitive material 140 isremoved, then the part of the UBM layer 130 not covered by the bump 120is etched. The step of removing the photosensitive material 140 can beperformed before or after the step of reflowing the second metal layer152, and the sequence of the manufacturing process can be designed tofit actual needs. In the present embodiment of the invention, the bump120 is completed by reflowing the second metal layer 152 first andremoving the photosensitive material 140.

Referring to FIG. 6, the semiconductor device 100 includes a pluralityof bonding pads 110 and bumps 120. Each of the bumps 120 corresponds toeach of the bonding pads 110, and the directions C1 in which the bumps120 extend from the bonding pads 110 are substantially parallel to eachother.

The bonding pads 110 are arranged along a line L110. The bumps 120extend in the same direction C1 from the bonding pads 110. The pitchG120 between the bumps 120 still remains approximately the same with thepitch G110 between the bonding pads 110 without significant reduction.Thus, under the circumstance that the pitch G120 between the bumps 120is not reduced, the bumps 120 formed according to the structural designand manufacturing method thereof disclosed in the above embodiment havebetter structural strength.

Beside, a plurality of trace contact points (not illustrated in thediagram) can be disposed on the flip-chip carrier corresponding to thebump 120 to be electrically connected with the bump 120. Compared withthe bumps, the contact points are outwardly disposed on the flip-chipcarrier in a fan-out arrangement or a fan-in arrangement. The distancebetween the contact points disposed on the flip-chip carrier is largerthan the distance between the bonding pads 110 disposed on the activesurface. That is, in prior arts, the bonding pads disposed on the activesurface 100 a are arranged in a line, and the contact points disposed onthe flip-chip carrier are positioned directly above the line to form theother line. In the present embodiment of the invention, the contactpoints disposed on the flip-chip carrier contact the bumps disposed onthe die and form electrical connection with thereto. Due to the shape ofthe extension of the bump 120, the contact points disposed on theflip-chip carrier do not need to form another line directly above theline formed by the bonding pads disposed on the active surface, butrather the contact points disposed on the flip-chip carrier can bearranged in a line not directly above the line formed by the bondingpads disposed on the active surface, or can be arranged not in a line.Further, as applied in a memory module, the connecting lines of theboding pads 110 and the bumps 120 disclosed in the embodiment of thepresent invention are disposed in an off-centered arrangement. And thebumps 120 can extend toward various directions and connect with thecontact points disposed on a flip-chip carrier. Therefore, the bondingpads 110 disposed on the active surface 100 a would not be disposed inonly one line, but can be disposed in two lines or a non-straight line.

The structural design of the shape of the extension of the bump 120 inthe present invention can replaces the conventional way of extending thelength of the bonding pad for enabling the non-extendable bump tocontact the contact points disposed on the flip-chip carrier. Furtherwith the arrangement of the contact points, such as the fan-outarrangement, the distance between the contact points can be furtherenlarged for the manufacturing process with lower requirements of wirewidth. Preferably, the distance between the contact points is largerthan the structure manufacturing process of 30 microns, but thetechnology of the invention is not limited thereto.

Second Embodiment

The semiconductor device 200 and manufacturing method thereof of thepresent embodiment of the invention differs with the semiconductordevice 100 and manufacturing method thereof of the first embodiment inthe disposition of the bump 220, and other similarities are not repeatedhere. Referring to FIG. 11, the disposition of a bump 220 of asemiconductor device 200 according to a second embodiment of theinvention is shown. In the present embodiment of the invention, thesemiconductor device 200 includes a plurality of bonding pads 110 andbumps 220. Each of the bumps 220 corresponds to each of the bonding pads110, and the directions C1 and C2 in which the bumps 220 extend from thebonding pads 110 are substantially parallel to each other. The bondingpads 110 are arranged along a line L110, and the bumps 220 alternatelyextend in opposite directions C1 and C2 from the bonding pads 110 toform a fan-out arrangement.

There is a larger pitch G220 between the bumps 220 extending in the samedirection C1. Likewise, there is a larger pitch G220 between the bumps220 extending in the same direction C2. The pitch G220 is equivalent tomore than two times the pitch G110 of the bonding pad 110. Therefore,during the assembly of the semiconductor device 200, the bump 220 andthe flip-chip carrier are more easily connected electrically, hencepreventing the shortcircuit between neighboring bumps.

Like the first embodiment, a plurality of trace contact points (notillustrated in the diagram) are disposed on the flip-chip carriercorresponding to the bump 220 for electrically connecting the top part(the solder) of the bump 220. Compared with the bump, the contact pointsare outwardly disposed on the flip-chip carrier in a fan-outarrangement. The distance between the contact points disposed on theflip-chip carrier is larger than the distance between the bonding pads110 disposed on the active surface. That is, in prior arts, the bondingpads disposed on the active surface are arranged in a line, and thecontact points disposed on the flip-chip carrier are positioned directlyabove the line to form the other line. In the present embodiment of theinvention, the contact points disposed on the flip-chip carrier contactthe bumps disposed on the die and form electrical connection withthereto. Due to the shape of the extension of the bump 220, the contactpoints disposed on the flip-chip carrier do not need to form the otherline directly above the line formed by the bonding pads disposed on theactive surface, but rather, the contact points disposed on the flip-chipcarrier can be arranged in a line not directly above the line formed bythe bonding pads disposed on the active surface, or can be arranged notin a line.

The structural design of the shape of the extension of the bump 220 inthe present invention can replace the conventional way of extending thelength of the bonding pad for the non-extendable bump to contact thecontact points disposed on the flip-chip carrier. Further with thearrangement of the contact points, such as the fan-out arrangement, thedistance between the contact points can be further enlarged for themanufacturing process with lower requirements of wire width.

Third Embodiment

The semiconductor device 300 and manufacturing method thereof of thepresent embodiment of the invention differs with the semiconductordevice 200 and manufacturing method thereof of the second embodiment inthe structural design of the bump 320, and other similarities are notrepeated here. Referring to FIG. 12, the disposition of a bump 320 of asemiconductor device 300 according to a third embodiment of theinvention is shown. In the present embodiment of the invention, the bump320 of the semiconductor device 300 has a substantially T-shapedcross-section parallel to the active surface 300 a.

As indicated in FIG. 12, after the T-shaped bump 320 substantiallyextends a first distance D31 in a first direction C31 from the bondingpad 110, the bump 320 extends a second distance D32 in a seconddirection C32 and a third direction C33 respectively. The first distanceD31 is longer than 1.2 times the width D110 of the bonding pad 110.

The cross-section of the bump is exemplified by an I-shaped structure ora T-shaped structure in the above embodiments. However, thecross-section of the bump can also be an elliptical structure or arectangular structure as long as the first dimension of the bump islonger than 1.2 times the second dimension. For example, in the T-shapedstructure, the two lines forming the T-shaped structure can have thesame length. However, the dimension of the length of the line divided bythe other line is not the physical dimension because the dimension ofthe length amounts to a smaller proportion of the overall dimension. Thephysical dimension is the average of the width. Meanwhile, the length ofthe extension of the bump is longer than 1.2 times the width of thebonding pad. Moreover, the bump does not need to completely cover thebonding pad, the bump only needs to cover part of the bonding pad, andsuch variation is still within the scope of technology of the invention.

In the above embodiments, the bump covers the bonding pad by the edge ofthe bump. However, the bump can also cover the bonding pad by thecentral part of the bump is within the scope of technology of theinvention as long as the area of the part of the active surface coveredby the bump is larger than 1.2 times the area of the bonding pad.Likewise, during the manufacturing process of the bump and asemiconductor device using the same, the bonding pad can also bepositioned at the central part of the opening.

In the semiconductor device and manufacturing method thereof disclosedin the above embodiments of the invention, the first dimension of thebump is longer than 1.2 times the second dimension, or the width of theextension of the bump is longer than 1.2 times the width of the bondingpad, such that the semiconductor device and manufacturing method thereofstill possess excellent structural strength under the restriction offine pitches. Thus, the semiconductor device and manufacturing methodthereof disclosed in the above embodiments of the invention at least hasthe following advantages:

Firstly, the structural strength is enhanced. The structural strength ofthe bump of the semiconductor device is greatly enhanced, hencepreventing the bump from being bent or shortcuited.

Secondly, the yield rate is improved. As the structural strength of thebump is enhanced, the semiconductor device is less likely to be defectedduring the process of assembly or removal, and the yield rate is thusimproved.

Thirdly, the manufacturing cost is reduced. During the manufacturingprocess, there is no need to input large amount of labor and materialfor inspection or re-work and the defected products are largely reduced,so the manufacturing cost is largely reduced.

While the invention has been described by way of example and in terms ofa preferred embodiment, it is to be understood that the invention is notlimited thereto. On the contrary, it is intended to cover variousmodifications and similar arrangements and procedures, and the scope ofthe appended claims therefore should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements and procedures.

What is claimed is:
 1. A column structure extending vertically from asemiconductor device for connecting to a carrier, comprising: a pillarpart having a first dimension and a second dimension, wherein the firstdimension is longer than the second dimension; and a top part disposedon the pillar part, wherein the pillar part comprises materials thatwill not melt under a pre-determined temperature and top part comprisesmaterials that will melt under the pre-determined temperature, whereinthe pillar part is formed on a bonding pad having a geometric center,metallization layer connects the bonding pad and the pillar part, andthe geometric center of the bonding pad is not aligned vertically withthe center of the pillar part.
 2. The column structure according toclaim 1, wherein the first dimension is the maximum dimension and thesecond dimension is the minimum dimension.
 3. The column structureaccording to claim 1, wherein the first dimension is perpendicular tothe second dimension.
 4. The column structure according to claim 1,wherein the first and second dimensions are parallel to a cross-sectionof the pillar part.
 5. The column structure according to claim 4,wherein the cross-section of the pillar part has an elliptical orrectangular shaped structure.
 6. The column structure according to claim4, wherein the cross-section of the pillar part composes of at least twolines, each line having a length and a width.
 7. The column structureaccording to claim 6, wherein the lines extend in different directions.8. The column structure according to claim 6, wherein the cross-sectionof the pillar part has a T-shaped structure or an I-shaped structure. 9.The column structure according to claim 1, wherein the pillar partcomprises copper (Cu), gold (Au), nickel (Ni) or a combination thereof.10. The column structure according to claim 1, wherein the top partcomprises tin (Sn), silver (Ag), lead (Pb) or a combination thereof. 11.The column structure according to claim 1, wherein the column structurecompletely covers the bonding pad.
 12. The column structure according toclaim 1, wherein the column structure is disposed on part of the bondingpad.
 13. A package structure, comprising: a semiconductor device havinga contacting position; a carrier having a contact point; and a columnstructure comprising a pillar part and a top part, and disposed betweenthe semiconductor device and the carrier, wherein the pillar part isconnected to the contacting position and the top part is connected tothe contact point, the pillar part comprises materials that will notmelt under a pre-determined temperature and top part comprises materialsthat will melt under the pre-determined temperature, wherein the pillarpart is formed on a bonding pad having a geometric center, ametallization layer connects the bonding pad and the pillar part, andthe geometric center of the bonding pad is not aligned vertically withthe center of the pillar part.
 14. The package structure according toclaim 13, wherein the first dimension is the maximum dimension and thesecond dimension is the minimum dimension.
 15. The package structureaccording to claim 13, wherein the first dimension is perpendicular tothe second dimension.
 16. The package structure according to claim 13,wherein the first and second dimensions are parallel to a cross-sectionof the pillar part.
 17. The package structure according to claim 16,wherein the cross-section of the pillar part has an elliptical orrectangular shaped structure.
 18. The package structure according toclaim 13, wherein the column structure completely covers the bondingpad.
 19. The package structure according to claim 13, wherein the columnstructure is disposed on part of the bonding pad.
 20. The packagestructure according to claim 13, wherein a center of the columnstructure is offset from a center of the bonding pad.
 21. The packagestructure according to claim 13, wherein a center of the bonding pad isoffset from a center of the contact point.
 22. The package structureaccording to claim 13, wherein a center of the column structure isoffset from a center of the contact point.
 23. The package structureaccording to claim 13, wherein the metallization layer comprises anadhesive layer, a barrier layer or a wetting layer.
 24. The packagestructure according to claim 13, wherein the pillar part comprisescopper (Cu), gold (Au), nickel (Ni) or a combination thereof.
 25. Thepackage structure according to claim 13, wherein the top part comprisestin (Sn), silver (Ag), lead (Pb) or a combination thereof.